* IEEE 1149.1 JTAG-compatible Boundary Scan
* 1.8 V or 2.5 V core power supply
* 1.8 V or 2.5 V I/O supply
* LBO pin for Linear or Interleaved Burst mode .

* JEDEC-standard 165-bump FP-BGA package
* RoHS-compliant 165-bump BGA package available Functional Description .

Applications The GS832118/32/36E-xxxV is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now fi.

GS832136GE

GS832136E

GS832136E-V

GS832132E

GS832132E-V

GS832132GE

GS832132GE-V

GS832118E

GS832118E-V

GS832118GE

GS832118GE-V

GS8321E18E

GS8321E18E-V

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